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MITSUBISHI SOUND PROCESSOR MITSUBISHI SOUND PROCESSOR ICsICs
M65824FP M65824FP SIGNAL PROCESSOR FOR CD PLAYER WITH BUILT-IN D/AD/A SIGNAL PROCESSOR FOR CD PLAYER WITH BUILT-IN
DESCRIPTION The M65824FP is a CMOS IC for playback of a compact disk (CD-DA). It is equipped with memory, non-adjustment PLL, 4fs digital filter and D-A converter. The M65824FP can configure a compact CD-DA system.
FEATURES
*Non-adjustment EFM-PLL with wide lock-range (built-in VCO) *Jitter margin 8 frames *Operatable CLV servo command *Attenuation (-12 dB) *Built-in 4fs digital filter *Built-in digital de-emphasis circuit *Built-in D-A converter *Compact set by the adoption of a compact package *Built-in analog LPF *External D-A mode
RECOMMENDED OPERATING CONDITIONS
Supply voltage range (interface)........................ DVDD = 2.7 to 5.5V Supply voltage range (internal circuit, analog) ............ DSPS, AVDD = 2.7 to 3.3V Rated supply voltage (interface).................................. DVDD = 5.0V Rated supply voltage (internal circuit, analog) ....................... DSPS, AVDD = 3.0V Rated power consumption.................................................. 100 mW
Outline 42P2R-A
0.8mm pitch 450mil SSOP (8.4mm x 17.5mm x 2.0mm)
SYSTEM CONFIGURATION M65824FP
SUBCODE INTERFACE Display
M
OPTICAL PICK-UP
RF-AMP PICK-UP SERVO AUTO ADJUSTMENT
PLL SLICER
EMF DE-MODULATOR
INTER POLATION
DEEMP
PLL CLK OSC CLK 18KSRAM CLV DIGITAL SERVO ECC C1:2error C2:2error MCU I/F
4FS DIGITAL FILTER
MOTOR DRIVER
D/A
L R
SYSTEM CONTROL MICROPROCESSOR
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MITSUBISHI SOUND PROCESSOR ICs
M65824FP
SIGNAL PROCESSOR FOR CD PLAYER WITH BUILT-IN D/A
BUILT-IN FUNCTIONS
*D/A converter *Memory *PLL block *64fs 1 bit D-A converter *S/N:74dB (typ.)
AVSS 1 WDCK 2 LOCK/DRD 3 CKSEL 4 ACLRB 5 C423 6 C846 7 XI 8 DVSS 9 XO 10 TEST 11 SBCO 12 SCCK 13 SYCLK 14 EFFK 15 KILLB 16 EST1 17 EST2 18 HF 19 TLC 20 LPF 21 42 AVDD 41 IREF 40 RNEG/LRCK 39 ROUT/DSCK 38 LNEG/WDCK 37 LOUT/DO 36 AMPREF 35 CGREF 34 EXP2 33 EXP1 32 MLAB 31 MSD 30 MCK 29 PWM2 28 PWM1 27 PWM 26 SCAND 25 CRCF 24 SBQS 23 DSPS 22 DVDD
PIN CONFIGURATION (TOP VIEW)
*Built-in 18K SRAM *Jitter margin 8 frames *Built-in non-adjustment VCO (Bit clock reproduction) * Non-adjustment slice level control
*EFM demodulator
*EFM modulation *Frame sync detection/protection and insertion *Frame monitor output
*Subcode modulator
*Modulation of subcodes P to W. serial output (conforming to EIJA CP-309) *Subcode Q register *CRC check *Subcode sync signal output (S0/S1)
*CIRC block
*Emphasis detection, built-in deemphasis control *C1: double correction, C2: double correction *Unscramble *De-interleave
*Interpolation processing unit
*Error monitor output *Average value interpolation and prevalue hold
Outline 42P2R-A *D-A interface *Digital filter *De-emphasis block
*Mute control *Quadruple over sampling I I R type filter *Bi-primary I I R filter *Emphasis detection/automatic operation
*CLV servo block
*PWM output *Reduced disk rotation detection output
*Microcomputer I/F block
*CLV servo control command *Mute control *-12 dB attenuation *Subcode Q register interface
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MITSUBISHI SOUND PROCESSOR ICs
M65824FP
SIGNAL PROCESSOR FOR CD PLAYER WITH BUILT-IN D/A
PIN DESCRIPTION
Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Symbol AVSS WDCK LOCK/DRD CKSEL ACLRB C423 C846 XI DVss XO TEST SBCO SCCK SYCLK EFFK KILLB EST1 EST2 HF TLC LPF DVDD DSPS SBQS CRCF SCAND PWM PWM1 PWM2 MCK MSD MLAB EXP1 EXP2 CGREF AMPREF LOUT/DO LNEG/WDCK ROUT/DSCK RNEG/LRCK IREF AVDD
I/O O O I I O O I O I O I O O O O O I O I/O O O O O O O I I/O I I I I I O O O O I -
Function Analog system GND Word clock output: f=88.2kHz Sync status/reduced disk rotation detection output System clock select input, "L": 8.4672 MHz/"H": 16.9344 MHz System reset input: reset="L" Crystal system 4.2336 MHz clock output Crystal system 8.4672 MHz clock output Crystal oscillator input (built-in feedback resistance) CKSEL="L": 8.4672MHz/CKSEL="H": 16.9344MHz Digital system GND Crystal oscillator output Shipment test pin: For test="H" Subcode serial output Subcode read clock input Frame sync output: Lock="H" .. PLL system frame clock output: duty=50% Digital silence output: Silence="L" open drain output Error status output 1: at C1 error detection="H" Error status output 2: at C2 error detection="H" Playback signal input Slice level control output PLL loop filter connection terminal Power supply to I/O block Power supply to internal logic circuit Subcode Q register read interrupt signal: Read enable: "L" CRC result of subcode Q: CRC OK="H" Subcode sync signal output: Synchronization="H" Disk motor drive PWM output (both sides) Disk motor drive PWM output 1 (acceleration side) Disk motor drive PWM output 2 (deceleration side) Microcomputer I/F shift lock Microcomputer I/F serial data I/O Microcomputer I/F latch clock (built-in 22k pull-up resistance) Additional microcomputer input port 1 (built-in 4.7k pull-up resistance) Additional microcomputer input port 2 (built-in 4.7k pull-up resistance) Current source reference current input pin for LPF Operation amplifier reference voltage setting pin for LPF L-ch audio signal output/serial data output (in external D-A mode) L-ch current source output/word clock output (in external D-A mode) R-ch audio signal output/data shift clock output (in external D-A mode) R-ch current source output/L-R clock output (in external D/A mode) Detection/PLL circuit reference current input Analog system power supply
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MITSUBISHI SOUND PROCESSOR ICs
M65824FP
SIGNAL PROCESSOR FOR CD PLAYER WITH BUILT-IN D/A
ABSOLUTE MAXIMUM RATINGS (Ta=25C, unless otherwise noted)
Parameter Supply voltage (I/O) AVDD-AVSS Supply voltage (analog) DSPS-DVSS Supply voltage (internal circuit) VI Input voltage Output voltage Vo Power dissipation Pd Topr Operating temperature Tstg Storage temperature
DVDD-DVSS
Symbol
Ratings -0.3 to +6.5 -0.3 to +3.6 -0.3 to +3.6 DVDD-0.3ViDVDD+0.3 DVSSVoDVDD 350 -10 to +70 -40 to +125
Unit V V V V V mW
C C
RECOMMENDED OPERATING CONDITIONS
Symbol DVDD AVDD DSPS VIH VOL fosc fvco Parameter Supply voltage (I/O) Supply voltage (analog) Supply voltage (internal circuit) Input voltage ("H" level) Output voltage ("L" level) Oscillation frequency Oscillation frequency Test conditions Min. 2.7 2.7 2.7
DVDD*0.7
Limits Typ. 5.0 3.0 3.0 8.4672 8.6436
Max. 5.5 3.3 3.3 DVDD
DVSS*0.3
Unit V V V V V MHz MHz
DVSS -
-
ELECTRICAL CHARACTERISTICS (Ta=25C, VDD=5V, unless otherwise noted)
Symbol IDD VOH VOL IIH IIL Parameter Circuit current Output voltage ("H" level) Output voltage ("L" level) Input voltage ("H" level) Input voltage ("L" level) Test conditions fosc=8.4672MHz fvco=8.6436MHz DVDD=5.0V IOH=-1.0mA DVDD=5.0V IOL=1.0mA VIH=4.5 VIL=0.5V Min. 4.5 -2 Limits Typ. 20 Max. 0.4 2 Unit mA V V A A
POWER SUPPLY
VDD:3.6 to 5.5V VDD:2.7 to 3.3V M65824FP M65824FP VDD:2.7 to 3.3V
DVDD 22 DSPS 23 AVDD 42
DVDD 22 DSPS 23 AVDD 42
Fig.1 3.0V system application example (supply voltage range of 2.7V to 3.3V)
Fig.2 5.0V system application example (two power supplies are required)
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MITSUBISHI SOUND PROCESSOR ICs
M65824FP
SIGNAL PROCESSOR FOR CD PLAYER WITH BUILT-IN D/A
FUNCTION DESCRIPTION
1. MICROCOMPUTER INTERFACE (1) Pin assignments M65824FP 31 CD-DA 30 MLAB O MSD I/O MCK O (2) Description MLAB: Latch signal/data I/O switching signal (MLAB="H":Write from P) (MLAB="L":Read from P)
P
SIGNAL PROCESSOR 32
MCK: Clock signal MSD: Serial data I/O
(3) Operation description * Microcomputer command read/write Data (MSD) is read at a rising edge of the clock pulse (MCK). When a command is determined at a falling edge of the latch line (MLAB), the data line (MSD) is concurrently switched to the output mode to output a status requested by data bits D3, D2, D1 and D0. When the latch line is set to "H", the data line is returned to the input mode again. *Status request/interface command When requesting various types of the M65824FP status, a microcomputer writes data in D3, D2, D1 and D0 for indicating the requested status in advance. After this command is latched, the status is continuously output while the latch line (MLAB) is set to "L".
(4) Microcomputer I/F timing chart
MSD
D0
D1
D2
D3
D4
D5
D6
D7
Status
MCK t1 MLAB t2 t3 t4
Symbol t1 t2 t3 t4
Parameter Shift clock width Shift clock setup Shift clock hold Shift clock setup
Min. 200 100 100 100
Unit nsec nsec nsec nsec
(5) M65824FP command list D7 Disk motor D6 D5 D4 D3
Initial value after power is turned on: 00000000 D2 D1 D0
Audio function
Status/interface command
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MITSUBISHI SOUND PROCESSOR ICs
M65824FP
SIGNAL PROCESSOR FOR CD PLAYER WITH BUILT-IN D/A
(6) Detailed data
1
Disk motor control D7 0 0 1 1 D6 0 1 0 1 Function Disk motor off
Accelerates the disk motor. Applies the maximum acceleration voltage to the motor. Decelerates the disk motor. Applies the maximum deceleration voltage to the motor.
Disk motor CLV control
2
Audio functions D5 0 0 1 1 D4 0 1 0 1 Function Muting Muting release Reserved 12 dB attenuation
3
Status/interface command D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Function Detects reduced disk rotating speed. "L" when the disk rotating speed is 2/3 or more of the normal speed. PLL lock status. "L" at locked. Subcode read status. "L" when new subcode is received External D-A mode (In case of input after reset) 33 Logical value of EXP1 (pin 33 ) Logical value of EXP2 (pin 34 ) Reserved Reserved PLL loop close (= HFD: "L") PLL loop open (= HFD: "H") Reserved Reserved Reserved Reserved Reserved Reserved When the subcode ready status is set to "L", a clock is sent with the latch line (MLAB) kept set to "L" to read the data of subcode Q from the internal register. Read all subcode Q data from the rising edge of SBQS until the next rising edge (for approximately 13.1 msec).
(7) Subcode Q register interface Data of subcode Q is stored in the internal 80-bit register and can be read using a microcomputer. Subcode ready status command is written to read subcode Q using a microcomputer. (MSD DATA 0100xxxx)
SBQS
typ.13.1msec B1 B2 B3 B4 B5 B6 B7 B8 B9 BA
MSD
MSD
Don't care
Status
Q1
Q2 Q3
Q4
Q5
Q6 Q7
Q8
Q9 Q10 Q11
Q12~Q79 Q80
MCK t5 MLAB t5: Mode setup time (min. 200 nsec) *SBQS is set to "L" when both the following two conditions are satisfied at the same time. (a) CRC check OK (b) When the two subcode syncs (S0, S1) are normal *A microcomputer can read information on subcode Q using the M65824FP only when SBQS is set to "L".
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MITSUBISHI SOUND PROCESSOR ICs
M65824FP
SIGNAL PROCESSOR FOR CD PLAYER WITH BUILT-IN D/A
2. DISK MOTOR CONTROL PULSE (CLV mode)
22.6757sec PWM1 (ACCELERATION) Min : 0.2362sec Max : 15.117sec 22.6757sec
PWM2 (DECELERATION) Min.: 0.2362sec Max.: 15.117sec 22.6757sec
(DECELERATION)
PWM (BOTH SIDES)
Hi-Z
(ACCELERATION)
Min.: 0.2362sec Max.: 15.117sec
Min.: 0.2362sec Max.: 15.117sec
22.6757sec
3. DIGITAL FILTER 0 Rejection band (f24 kHz) Attenuation -36 dB -20 -36 -40 -2 Passing band (f20 kHz) Ripple 0.6 dB 0 -0.6
-4
-60
-6
-80
-8
-100
0
20
40
60
80
100
-10
0
20
40
60
80
100
FREQUENCY (kHz)
FREQUENCY (kHz)
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MITSUBISHI SOUND PROCESSOR ICs
M65824FP
SIGNAL PROCESSOR FOR CD PLAYER WITH BUILT-IN D/A
APPLICATION EXAMPLE
1 2 3 4 5 6 7 8 9
AVSS WDCK LOCK/DRD CKSEL ACLRB C423 C846 XI DVSS
AVDD 42 IREF 41 RNEG/LRCK 40 Audio R ROUT/DSCK 39 LNEG/WDCK 38 LOUT/DO 37 AMPREF 36 CGREF 35 EXP2 34 EXP1 33 MLAB 32 MSD 31 MCK 30 PWM2 29 PWM1 28 PWM 27 SCAND 26 CRCF 25 SBQS 24 DSPS 23 DVDD 22 Disc Motor Driver Microcomputer Audio L LPF LPF
10 XO 11 TEST 12 SBCO 13 SCCK 14 SYCLK SUBCODE I/F 15 EFFK 16 KILLB 17 EST1 18 EST2 19 HF 20 TLC 21 LPF
HF INPUT
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